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DDR Memory Power Supply Controller
POWER MANAGEMENT Description
The SC1480 is a single output, constant on-time synchronous-buck, pseudo-fixed frequency, PWM controller intended for use in notebook computers and other battery operated portable devices. Features include high efficiency and fast dynamic response with no minimum on time, a reference input and a buffered REFOUT pin capable of sourcing 3mA. The excellent transient response means that SC1480 based solutions will require less output capacitance than competing fixed frequency converters. The frequency is constant until a step in load or line voltage occurs, at which time the pulse density and frequency will increase or decrease to counter the change in output or input voltage. After the transient event, the controller frequency will return to steady state operation. The SC1480 incorporates two power-reducing states, standby and shutdown. In standby mode, the switcher output is shutdown but the buffered reference output stays up, reducing quiescent current to a low 125A. This is particularly useful for reducing battery draw in systems which implement a suspend-to-RAM (S3) state. The SC1480 can be completely shut down, drawing less than 10A. The integrated gate drivers feature adaptive shootthrough protection and soft switching. Additional features include cycle-by-cycle current limit, digital soft-start, overvoltage and under-voltage protection, and a PGOOD output.
SC1480
Features
Constant on-time for fast dynamic response Programmable VOUT based on external reference VIN range = 1.8V - 25V DC current sense using low-side RDS(ON) sensing or sense resistor 3mA reference output buffer Low power S3 state Resistor programmable frequency Cycle-by-cycle current limit Digital soft start Output current source-sink capability Overvoltage/under-voltage fault protection and PGOOD output Under 10uA typical shutdown current Low quiescent power dissipation 14-Pin TSSOP package. Also available in Lead-free package which is fully WEEE and RoHS compliant Industrial temperature range Integrated gate drivers with soft switching Efficiency >90%
Applications
Notebook computers CPU I/O supplies Handheld terminals and PDAs LCD monitors Network power supplies
Typical Application Circuit
4.5V - 25V VDD = 2.5V +5VRUN C1
R1 REFOUT C3 +5VSB R2 R3 +5V R4 1 2 3 4 5 6 7 C8 C9 U1 BST REFIN DH TON REFOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND SC1480 R7 C4
C2 D1
C5 Q1 14 13 12 11 10 9 8 C10 L1 1.25VOUT R6 Q2 D2 + C6 C7
R5
PGOOD
Revision: August 30, 2006
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SC1480
POWER MANAGEMENT Absolute Maximum Ratings
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Pin Combination TON to AGND DH, BST to AGND LX to AGND AGND to PGND BST to LX VCCA, VDDP to AGND FB, PGOOD, REFIN, ILIM, REFOUT, DL to PGND Thermal Resistance, Junction to Ambient(4) Operating Junction Temperature Range Storage Temperature Range Lead Temperature (Soldering) 10 Sec.
Symbol
Maximum -0.3 to +25.0 -0.3 to +30.0 -2.0 to +25.0 -0.3 to +0.3 -0.3 to +6.0 -0.3 to +6.0 -0.3 to +6.0
Units V V V V V V V C/W C C C
JA TJ TSTG TLEAD
100 -40 to +125 -65 to +150 300
Electrical Characteristics
Test Conditions: VIN = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M (300kHz), 0.1% Resistor Dividers
Parameter
Conditions Min
25C Typ Max
-40C to 125C Min Max
Units
Input Supplies VCCA Input Voltage VDDP Input Voltage VIN Input Voltage VDDP Operating Current VCCA Operating Current VCCA Standby Current TON Operating Current Shutdown Current (REFIN = 0V) VC C A VDDP + VIN Controller Error Comparator Threshold (FBK Turn-on Threshold) (1)
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5.0 5.0 2.0 FB > regulation point, ILOAD = 0A FB > regulation point, ILOAD = 0A VDDP < VDDP UV Threshold No Load On REFOUT RTON = 1M (300kHz) 5 700 125 15 25
4.5 4.5
5.5 5.5
V V V
10 1100
A A A A
5 5
10 10
A A
With Respect to REFOUT VCCA = 4.5V to 5.5V
2
REFOUT
REFOUT REFOUT -10 +10
mV
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SC1480
POWER MANAGEMENT Electrical Characteristics Cont.
Test Conditions: VIN = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M (300kHz), 0.1% Resistor Dividers
Parameter
Conditions Min
25C Typ 1660 913 400 Max
-40C to 125C Min 1411 776 Max 1909 1050 550
Units
On-Time
RTON = 1M (300kHz) VIN = 2.5V RTON = 500K (600kHz) VIN = 2.5V
ns ns ns %/V % k
Minimum Off Time Line Regulation Error Load Regulation Error FBK Input Resistance Over-Current Sensing ILIM Sink Current Current Comparator Offset Reference Buffer REFOUT Source Current REFIN Enable Threshold REFIN Hysteresis Offset Voltage REFOUT current = 0mA REFOUT current = 3mA Fault Protection Current Limit (Positive) (2) PGND-LX, RILIM = 5k PGND-LX, RILIM = 10k PGND-LX, RILIM = 20k Current Limit (Negative) Output Under-Voltage Fault Output Over-Voltage Fault Over-Voltage Fault Delay PGOOD Low Output Voltage PGOOD Leakage Current PGOOD UV Threshold PGND-LX With respect to REFOUT With respect to REFOUT FBK forced above OV Vth Sink 1mA FBK in regulation, PGOOD = 5V With respect to REFOUT PGND - ILIM VCCA, VDDP = 4.5V to 5.5V Vin = 4.5V to 25V ILIM - PGND = 0V to 0C Limit
0.04 0.3 500
10
9 -5
11 5
A mV
3 0.8 40 -10 -12.5 10 12.5 0.55 1.0
mA V mV mV mV
50 100 200 -140 -20 +10 2.0
40 90 180 -200 -28 +8
60 110 220 -100 -15 +12
mV mV mV mV % % s
0.4 1 -10 -12 -8
V A %
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SC1480
POWER MANAGEMENT Electrical Characteristics Cont.
Test Conditions: VIN = 2.5V, REFIN = 1.25, VCCA = VDDP = 5.0V, VOUT = 1.25V, RTON = 1M (300kHz), 0.1% Resistor Dividers
Parameter
Conditions Min
25C Typ 2.0 4.0 3.3 250 Max
-40C to 125C Min Max
Units
PGOOD Fault Delay VCCA Under Voltage Threshold VDDP Under Voltage Threshold VDDP Under Voltage Hysteresis Over Temperature Lockout Soft Start Soft-Start Ramp Time Under-Voltage Blank Time Gate Drivers Dead Time DL Pull-Down Resistance DL Pull-Up Resistance DH Pull-Down Resistance DH Pull-Up Resistance DL Sink Current DL Source Current DH Sink Current DH Source Current
FB forced outside PGOOD window. Rising Edge Hysteresis 100mv
s 3.7 3.0 4.3 3.75 V V mV C
10C Hysteresis
165
REFIN high to full current limit. SMPS Turn-On
1.6 2
ms ms
DH or DL rising DL low DL high DH low, BST - LX = 5V DH high, BST - LX = 5V DL - PGND = 2.5V VDDP - DL = 2.5V DH - LX = 2.5V, BST - LX = 5V BST - DH = 2.5V, B S T - LX = 5V
30 0.8 2 2 2 2 1 1 1 1.6 4 4 4
ns A A A A
Notes: (1) When the inductor is in continuous conduction mode, the output voltage will have a DC regulation level higher than the error-comparator threshold by 50% of the ripple voltage. (2) Using a current sense resistor, this measurement relates to PGND minus the voltage of the source on the low-side MOSFET. (3) This device is ESD sensitive. Use of ESD handling precautions is required. (4) Measured in accordance with JESD51-1, JESD51-2 and JESD51-7.
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SC1480
POWER MANAGEMENT Pin Configuration Ordering Information
Device
(1)
TOP VIEW
REFIN TON REFOUT VCCA FBK PGOOD AGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 BST DH LX ILIM VDDP DL PGND
P ackag e TSSOP-14 TSSOP-14 Evaluation Board
SC1480ITSTR SC1480ITSTRT(2) S C 1480E V B
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant.
(14 Pin TSSOP)
Pin Descriptions
Pin # 1 2 3 4 5 6 7 8 9 10 11 Pin Name REFIN TON REFOUT VC C A FB K PGOOD AGND PGND DL VD D P ILIM Pin Function External Reference input. Tie to ground to disable SMPS and reference buffer. On-time set input. Sets on-time of upper MOSFET via series resistor to the input supply. Reference output pin. Can source 3mA. Supply voltage input for the analog supply. Connect through a RC filter to +5V. Feedback input. Connect from resistor divider at output of SMPS to select output voltage. Power Good open drain NMOS output. Goes high after a fixed clock cycle delay following power up. Analog ground. Power ground. Gate drive output for the low side MOSFET switch. +5V supply voltage input for the gate drivers. Tie to ground to disable SMPS. Current limit input. Connect to drain of low-side MOSFET for RDS(on) sensing or the source for resistor sensing through a threshold sensing resistor. See applications section for more information. Switching node inductor connection. Gate drive output for the high side MOSFET switch. Boost capacitor connection for the high side gate drive.
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12 13 14
LX DH BST
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SC1480
POWER MANAGEMENT Block Diagram
VDDQ = 2.5V
VCCA
VDDQ REFIN 1
VDDP
OT 14 BST HI 13 DH 12 LX
VDDP
VDDQ
POR/SS
2 VIN +5V REFOUT 3 4 VCCA REFOUT
TON
ON OFF PWM
CONTROL LOGIC
VOUT
TOFF
REF BUFFER OC ISENSE ZEROI 11 ILIM
VOUT
5 FBK
+ -
+ PWM +5V
10 VDDP 6 PGOOD 7 AGND FAULT MONITOR OV UV LO 9 DL 8 PGND
REF+10% REF-10% REF-20%
FIGURE 1
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SC1480
POWER MANAGEMENT Applications Information
+5V Bias Supply The SC1480 requires an external +5V bias supply in addition to the battery. If stand-alone capability is required, the +5V supply can be generated with an external linear regulator. There are two inputs for the external +5V bias supply, VCCA & VDDP. The VCCA input powers the analog section of the SC1480 while the VDDP input provides power to the upper and lower gate drivers. VCCA will need to be decoupled from the +5V supply through a 10 Ohm resistor and the addition of a filter capacitor from VCCA to ground. VCCA and VDDP must be separate in order to utilize the low power S3 state of the SC1480. The battery input VIN and the +5V input VCCA can be tied together if the input voltage is fixed from +4.5V to +5.5V; however, as before, VCCA will need to be decoupled from the +5V supply through a 10 Ohm resistor and the addition of a filter capacitor from VCCA to ground. Pseudo-Fixed Frequency Constant On-Time PWM Controller The PWM control architecture consists of a constant-ontime, pseudo fixed frequency PWM controller, (Figure 1). The output ripple voltage developed across the output filter capacitors ESR provides the PWM ramp signal eliminating the need for a current sense resistor. The highside switch on-time is determined by a one-shot whose period is directly proportional to output voltage and inversely proportional to input voltage. A second one-shot sets the minimum off-time to 400ns typically. On-Time One-Shot (TON) The on-time one-shot comparator has two inputs. One input looks at the output voltage, while the other input samples the input voltage and converts it to a current. This input proportional current is used to charge an internal on-time capacitor. The TON time is the time required for the voltage on the capacitor to charge from zero volts to VOUT, thereby making the on-time of the high-side switch directly proportional to output voltage and inversely proportional to input voltage. This implementation results in a nearly constant switching frequency without the need of a clock generator. RTON is a resistor connected from the input supply to the TON pin. The graph on page 19 shows the relationship between RTON and switching frequency. Reference I/O The reference input can be generated off of a 2.5V or VDDQ supply by a simple resistive divider. Resistors less than 100k Ohms should be used and a small filter capacitor from the reference input to ground of 0.1uF will remove any ripple voltage present on the input. The input has a common mode range of the REFIN threshold to 2.5V. The voltage on the reference input passes through a unity gain buffer prior to being sent to REFOUT. This reference output has a class A output stage with 3mA of sourcing capacity. It has a pull-down impedance of 50k. The output will require a small RC filter of 10 Ohms and 1F to maintain stability. Shutdown, Suspend to RAM and Run Mode The SC1480 has three modes of operation: shutdown, suspend to RAM, and run mode. All three modes must have VCCA connected at all times. Shutdown mode is controlled by REFIN. When REFIN is below 0.8V, the reference buffer will be off and the SMPS is disabled. In this mode the bias current of the device will be less than 10A. Suspend to RAM, or S3 State, is controlled by REFIN and VDDP. With REFIN is above 0.8V and VDDP is low (below 3V), the device will output the reference voltage onto REFOUT, but the SMPS is disabled. In this mode the bias current is approximately 125A. Run mode is activated by maintaining REFIN above 0.8V and VDDP above 3V. In this mode the reference and SMPS are active. Current Limit Circuit Current limiting of the SC1480 can be accomplished in two ways. First, the device can implement on-state resistance of the low-side MOSFET as the current sensing element (RDSON sensing). Second, the device can accept a resistive element in the low-side source (RSENSE, resistor sensing). The second method offers greater accuracy of the current limit threshold over RDSON sensing, at the added expense of a sense resistor and associated efficiency loss. Whether RDSON sensing or RSENSE resistor sensing is used,
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V TON = 3.3x10 -12 *(RTON + 37x10 3 ) * OUT V IN
+ 50S
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SC1480
POWER MANAGEMENT Applications Information (Cont.)
a scaling resistor between LX and ILIM is required. This resistor, RILIM, is connected to a 10A current source within the SC1480 through the ILIM pin. This sets a voltage drop equal to 10A times RILIM. As the current increases through the lower MOSFET, the phase pin voltage will decrease until the offset voltage caused by RILIM is reached and ILIM < PGND. At this point an overcurrent trip signal is issued. Current limiting will prevent the firing of a DH on-pulse, thereby reducing the switching frequency. As the frequency decreases, the output voltage will drop until an under-voltage shutdown is reached. The current sensing circuit actually limits the inductor valley current (see Figure 2). This means that if the current limit is set to 10A, the peak current through the inductor would be 10A plus the peak ripple current, and the average current through the inductor would be 10A plus 1/2 the peak-to-peak ripple current. The equations for setting the valley current and calculating the average current through the inductor are shown below:
+5V +VIN
D1
+
C1
BST DH LX ILIM VDDP DL PGND
14 13 12 11 10 9 8
C2
Q1 L1 VOUT
R1 Q2
SC1480
D2
+
C3 FBK
FIGURE 3
Schematic of RDSON sensing circuit is shown in Figure 3 with RDSON of Q2. Similarly, for resistor sensing, the current through the lower MOSFET and the source sense resistor develops a voltage that opposes the voltage developed across RILIM. When the voltage developed across the RSENSE resistor reaches voltage drop across RILIM, an overcurrent will be issued. The overcurrent equation when using an external sense resistor is:
IL OC (Valley ) = 10A *
RILIM RDS ON
IL 2
IL OC (Average) = IL OC (Valley ) +
IL OC (Valley ) = 10A *
INDUCTOR CURRENT IPEAK ILOAD
+5V
RILIM R SENSE
Schematic of resistor sensing circuit is shown in Figure 4 with RILIM = R1 and RSENSE = R2.
+VIN
ILIMIT
D1 + C1
TIME Valley Current-Limit Threshold Point
BST DH LX ILIM VDDP DL PGND
14 13 12 11 10 9 8
C2
Q1 L1 VOUT
Q2 + R1 D2 R2 FBK C3
SC1480
FIGURE 2
FIGURE 4
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SC1480
POWER MANAGEMENT Applications Information (Cont.)
Power Good Output Power good is an open-drain output and requires a pullup resistor. When the output voltage is 10% above or below its set voltage, PGOOD gets pulled low. It is held low until the output voltage returns to within 10% of the output set voltage. PGOOD is also held low during startup and will not be allowed to transition high until the output reaches 90% of its set voltage. There is a slight delay built into the PGOOD circuit to prevent false transitions. Output Overvoltage Protection When the output exceeds 10% of the its set voltage the low-side MOSFET is latched on. It stays latched and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the OV protection circuit to prevent false transitions. Output Undervoltage Protection When the output is 20% below its set voltage the output is latched in a tristated condition, and the SMPS is off until the enable input or POR is toggled. There is a slight delay built into the UV protection circuit to prevent false transitions. POR, UVLO and Softstart An internal power-on reset (POR) occurs when VCCA exceeds 3V, resetting the fault latch and soft-start counter, and preparing the PWM for switching. VCCA undervoltage lockout (UVLO) circuitry inhibits switching and forces the DL gate driver high until VCCA rises above 4.1V. At this time the circuit will come out of UVLO and begin switching, and the softstart circuit being enabled, will progressively limit the output current over a predetermined time period. The ramp occurs in four steps: 25%, 50%, 75% and 100%, thereby limiting the slew rate of the output voltage. There is 100mV of hysteresis built into the UVLO circuit and when the VCCA falls to 4.0V the output drivers are shutdown and tristated. MOSFET Gate Drivers The DH and DL drivers are optimized for driving moderate-sized high-side, and larger low-side power MOSFETs. An adaptive dead-time circuit monitors the DL output and prevents the high-side MOSFET from turning on, until DL is fully off, and conversely, monitors the DH output and prevents the low-side MOSFET from turning on until DH is fully off. Be sure there is low resistance and low inductance between the DH and DL outputs to the gate of each MOSFET.
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The high-side gate driver is equipped with turn-on soft switching to reduce gate drive power dissipation. When a DH turn-on is initiated the pull-up resistance is 10 Ohms. This limits the peak high-side gate current before the MOSFET is conducting current. The peak gate current plays a large role in gate driver switching losses. When the high-side MOSFET begins conducting, and LX starts to rise, the pull-up resistance on DH changes to 2 Ohms. Design Procedure Prior to any design of a switch mode power supply (SMPS) for notebook computers, determination of input voltage, load current, switching frequency and inductor ripple current must be specified. Input Voltage Range The maximum input voltage (VINMAX) is determined by the highest AC adaptor voltage. The minimum input voltage (VINMIN) is determined by the lowest battery voltage after accounting for voltage drops due to connectors, fuses and battery selector switches. Maximum Load Current There are two values of load current to consider. Continuous load current and peak load current. Continuous load current has more to do with thermal stresses and therefore drives the selection of input capacitors, MOSFETs and commutation diodes. Whereas, peak load current determines instantaneous component stresses and filtering requirements such as, inductor saturation, output capacitors and design of the current limit circuit. Switching Frequency Switching frequency determines the trade-off between size and efficiency. Increased frequency increases the switching losses in the MOSFETs, since losses are a function of VIN2. Knowing the maximum input voltage and budget for MOSFET switches usually dictates where the design ends up. Inductor Ripple Current Low inductor values create higher ripple current, resulting in smaller size, but are less efficient because of the high AC currents flowing through the inductor. Higher inductor values do reduce the ripple current and are more efficient, but are larger and more costly.
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SC1480
POWER MANAGEMENT Applications Information (Cont.)
The selection of the ripple current is based on the maximum output current and tends to be between 20% to 50% of the maximum load current. Again, cost, size and efficiency all play a part in the selection process. Design Example The following design example is for the evaluation board schematic shown on page 16. While most DDR supplies have a maximum load of 3A, the following design was meant for applications beyond DDR memory. Therefore, this design will have an input voltage from 5V to 19V, with an output voltage of 1.25V at 5A of load current. Inductor Selection The switching frequency is set to 300kHz which yields a good trade-off of size and efficiency. RTON is chosen to be 1M Ohm for a switching frequency of 300kHz. Because ripple voltage is used as the feedback mechanism of this device, this leads to the choice of the ripple current being 10% of load current. This will give a nice ripple voltage waveform for ensuring proper PWM triggering for this type of controller. RDSON of the MOSFET is a nominal 0.013 Ohms, accounting for increased temperature effects use 0.015 Ohm.
RILIM = 0.015 * 6.5 = 10k 10A
The inductor chosen was a Panasonic 4H, 11A inductor. Similarly, using a Sense resistor to obtain a more accurate current limit would make use of the valley current equation. Thus, for a 0.015 Ohm resistor the RILIM would calculate to the same 10k Ohm ILIM resistor will be 6 * 6 * 0.015 = 0.54 W effecting the efficiency budget. Output Capacitor Selection The output filter capacitor must have low effective series resistance (ESR) to meet the output ripple and load transient requirements, at the same time have high enough ESR to satisfy stability requirements. In addition, the value of output capacitance must be high enough to absorb the inductor energy going from full-load to noload without tripping the overvoltage protection circuit. For CPU load transients, how much ESR is needed depends upon output voltage variation limits under a CPU load transient. The ESR for this condition is given:
IL = 0.1*5 = 0.5A
L= VOUT * (VIN - VOUT ) * T VIN * IL
L = 4H
Setting the Current Limit The minimum current-limit threshold must be high enough to support the maximum load current. The valley of the inductor current occurs at:
ESR =
VOUT ILOAD(MAX)
ILoad(Max) -
IL 2
In non CPU applications, the output capacitor size depends on how much ESR is needed to maintain an acceptable level of output voltage ripple. Under these conditions the ESR value is given:
, (see Figure 2) therefore:
ESR =
VOUT(p - p) ILOAD(MAX)
ILIM(Low) > ILoad(Max) -
IL 2
The inductor must not saturate under all conditions of operation. If the current limit is set to 6.5A the maximum current through the inductor will be: 6.5 + IL = 7A Setting the over current to 6.5A is calculated as follows:
However, for most CPU applications the minimum capacitance required is limited by the energy absorption of the output capacitor. The equation for determining the minimum capacitance can be found by the following equation:
RILIM =
RDSON*ILOC 10A
CMIN =
LOUT *IOUT 2 VF 2 - VI2
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SC1480
POWER MANAGEMENT Applications Information (Cont.)
Where VF is the final output voltage after release of the load and VI is the initial voltage prior to the release of load. If no more than 100mV of output voltage variation is required between VF and VI , plugging in the numbers for the application circuit yields minimum output capacitance of 1000F. As shown, a large amount of capacitance is required to absorb the energy of the inductor during a load release of 5A. In typical DDR memory applications a load release of this magnitude is not an issue and therefore the application circuit can get by with 300F of output capacitance. Stability Considerations: Unstable operation shows up in two related but distinctly different ways: double pulsing and fast-feedback loop instability. Double-pulsing occurs due to noise on the output or because the ESR is too low, causing not enough voltage ramp in the output signal. This causes the error amplifier to trigger prematurely after the 400ns minimum off-time has expired. Double-pulsing will result in higher ripple voltage at the output, but in most cases is harmless. However, in some cases double-pulsing can indicate the presence of loop instability, which is caused by insufficient ESR. One simple way to solve this problem is to add some trace resistance in the high current output path. A side effect of doing this is output voltage droop with load. SC1480 ESR Requirements The constant on-time control used in the SC1480 regulates the ripple voltage at the output capacitor. This signal consists of a term generated by the output ESR of the capacitor and a term based on the increase in voltage across the capacitor due to charging and discharging during the switching cycle. The minimum ESR is set to generate the required ripple voltage for regulation. For most applications the minimum ESR ripple voltage is dominated by PCB layout and the properties of SP or POSCAP type output capacitors. For applications using ceramic output capacitors the absolute minimum ESR must be considered. Existing literature describing the ESR requirements to prevent double pulsing does not accurately predict the performance of constant on-time controllers. A time domain model of the converter was developed to generate equations for the minimum ESR empirically. If the ESR is low enough the ripple voltage is dominated by the charging of the output capacitor. This ripple voltage lags the on-time due to the LC poles and can cause double pulsing if the phase delay exceeds the off-time of the converter. Referring to Figure 3, the equation for the minimum ESR as a function of output capacitance and switching frequency and duty cycle is;
Fs - 200000 1+3 * Fs ESR > 2* *Cout *Fs * 1 -D 2 ( )
Where D = Vout/Vin. Plugging in the numbers for this design ESR > 0.004 Ohms. Input Capacitor Selection Input capacitors are selected based upon the input ripple current demand of the converter. First determine the input ripple current expected and then choose a capacitor to meet that demand. The input RMS ripple current can be calculated as follows:
IRMS = VOUT * (VIN - VOUT ) * IOUT VIN
Therefore, for a maximum load current of 6.0A , the input capacitors should be able to safely handle 3A of ripple current. For the EVAL board, we chose two 10F, 25V ceramic capacitors. Each capacitor has a ripple current capability of 2A. MOSFET Switch Selection The current selection of MOSFETs are determined by the setting of the overcurrent limit circuit and the maximum input voltage. The next step is to determine their power handling capability. For the EVAL board the ISi4484 meet the voltage and current requirements. This is a 30V, 10A FET. Based on 85C ambient temperature, 150C junction temperature and thermal resistance, their power handling is calculated as follows: Power Limit for Upper & Lower FET: TJ = 150C; TA = 85C; = 50C/W
JA
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SC1480
POWER MANAGEMENT Applications Information (Cont.)
PT = TJ - TA 150 - 85 = = 1.3W JA 50
Each FET must not exceed 1.3W of power dissipation. MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case conduction power dissipation occurs at minimum battery voltage:
performance, use the slowest on-time setting of 200kHz. When working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. The IC duty-factor limitation is given by:
DUTY =
TON(MIN) TON(MIN) + TOFF(MAX)
PDUC =
VOUT *ILOAD2 *RDS(ON) VIN(MIN)
Be sure to include inductor resistance and MOSFET onstate voltage drops when performing worst-case dropout duty-factor calculations. Layout Guidelines As with any high frequency switching regulator, it is advisable to practice a careful layout strategy. This includes keeping loop area as small as possible. And properly decoupling lines that pull large currents in short periods of time. To keep loop area small always use a ground plane and if possible split the plane in two areas, signal GND and power GND, then tie the two together at one point. Be sure that high current paths have low inductance by making trace widths wide where possible. The SC1480 pin-outs contain digital signals on the right and analog signals on the left side of the device. This facilitates the isolation of digital and analog signals enabling effective layout of the device. In summary follow these guidelines for good PC board layout::
Typically, a small high-side MOSFET is selected to reduce switching losses at high input voltages. However, the RDS(ON) limits how small the MOSFET can be. Another element of loss in the upper MOSFET is the switching loss, especially at high input voltages, those seen when the AC adaptor is applied. The upper MOSFET switching losses can be estimated as follows:
PDUS =
CRSS* VIN(MAX )2 * f *ILOAD IGATE
Where CRSS is the reverse transfer capacitance of the upper MOSFET and IGATE is the peak gate-drive source/ sink current which is approximately 1A for the SC1480. For the low-side MOSFET the there are only conduction loses to be concerned about since the commutation diode is active while the lower MOSFET switches. The worstcase power dissipation occurs at maximum battery voltage:
VOUT PDLC = 1 *ILOAD2 *RDS( ON) VIN(MAX )
Adding up the power dissipation for each MOSFET can now proceed and the total for each MOSFET should not exceed 1.3W which was calculated earlier to be the maximum power dissipation under worst-case conditions. Dropout Performance The output voltage adjust range for continuousconduction operation is limited by the fixed 500nS (maximum) minimum off-time one-shot. For best dropout
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* Keep high-current paths short, especially at the ground terminals. * Tie AGND and PGND together close to the IC. * Keep the power traces and load connections short. This practice is essential for high efficiency. Using thick copper PC boards (2oz vs 1oz) can enhance full-load efficiency by 1% or more. * Connect the ILIMIT resistor as close to the lower MOSFET drain as possible, and keep the resistance distance from the ILIM pin to the drain short. This will improve current limit accuracy.
1480 System DC Accuracy Two IC parameters effect system DC accuracy, the error comparator offset voltage, and the switching frequency variation with line and load. The 1480 regulates to the REFOUT voltage not the REFIN voltage. Since DDR specifications are written with respect to REFOUT, the offset of the reference buffer does not create a regulation error.
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SC1480
POWER MANAGEMENT Applications Information (Cont.)
The error comparator offset is trimmed so that it trips when VOUT is 1.25 volts +/-1% at room temperature. This offset does not drift significantly with supply and temperature. Thus, the error comparator contributes 1% or less to DC system inaccuracy. The on pulse in the SC1480 is calculated to give a pseudo fixed frequency. Nevertheless, some frequency variation with line and load can be expected. This variation changes the output ripple voltage. Because constant on regulators regulate to the valley of the output ripple, 1/2 of the output ripple appears as a DC regulation error. For example, if REFOUT=1.25 volts, then the valley of the output ripple will be 1.25 volts. If the ripple is 20mv with VIN=6, then the DC output voltage will be 1.26 volts. If the ripple is 40mv with VIN=25 volts, then the DC output voltage will be 1.27 volts. The best way to minimize this effect is to minimize the output ripple. To compensate for valley regulation it is usually desirable to use passive droop. Take the feedback directly from the output side of the inductor incorporating a small amount of trace resistance between the inductor and output capacitor. This trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. Passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced. Passive droop also improves stability so it should be used when possible. Thermal Considerations The junction temperature of the device may be calculated as follows:
TJ = TA + PD * JA C
Where: TA = ambient temperature (C) PD = power dissipation in (W) JA = thermal impedance junction to ambient from absolute maximum ratings (C/W) The power dissipation may be calculated as follows:
PD = VCCA * IVCCA + Vg * Q g * f
W
Where: VCCA = chip supply voltage (V) IVCCA = operating current (A) Vg = gate drive voltage, typically 5V (V) Qg = FET gate charge, from the FET datasheet (C) f = switching frequency (kHz) Inserting the following values as an example: TA = 85C JA = 100C/W VCCA = 5V IVCCA = 1100A (data sheet maximum) Vg = 5V Qg = 60nC f = 300kHz gives us:
TJ = 85 + 5 * 1100 * 10 -6 + 5 * 60 * 10 -9 * 300 * 10 3 * 100 = 95
(
)
C
As can be seen, the heating effects due to internal power dissipation are practically negligible, thus requiring no special consideration thermally during layout.
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SC1480
POWER MANAGEMENT Reference Design
+5V_RUN
C1 10uF/10V
4.5V - 25V 2.50V_SUS C2 10uF/25V
R1 20K REFOUT C3 1uF +5V_SUS R2 1M D1 ZHCS400 R3 20K Q1 8 U1 REFIN BST TON DH REFOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND SC1480 C8 0.01uF C5 0.1uF 14 13 12 11 10 9 8 2 1 5 6 7 4 Si4818DY 3 R6 10K
C4 1uF
+5V
R4 10 R5 1M 1 2 3 4 5 6 7 C6 1uF C7 1000pF
PGOOD R7 NO_POP
L1 1.25VOUT 4.1uH + C9 150uF
C10 10uF
VIN = 4.5V - 25V VOUT = 1.25V; IOUT = 3A
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SC1480
POWER MANAGEMENT Reference Design - Bill of Material
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Quantity 1 1 3 1 1 1 1 1 1 1 1 2 2 1 1 1 1 C1 C2 C3,C4,C6 C5 C7 C8 C9 C 10 D1 L1 Q1 R1, R3 R2, R5 R4 R6 R7 U1 Reference 10uF/10V 10uF/25V 1uF 0.1uF 1000pF 0.01uF 150uF 10uF ZHCS400 4.1uH S i 4818D Y 20k 1m 10 10k No Pop S C 1480 Part Vendor
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SC1480
POWER MANAGEMENT Evaluation Board Schematic
+5V TP1 +5V TP2 C1 10uF/6.3V 2 J1 5VRUN TP3 5VRUN TP4 C2 10uF/6.3V R4 10 GND J2 1 2 VIN R5 1M TP7 REFI +5V R6 1M TP9 RGND REFO TP8 C9 1uF C7 1uF U2 1 2 3 4 5 6 7 C13 1uF C14 1000pF R9 REFIN BST TON DH REFOUT LX VCCA ILIM FBK VDDP PGOOD DL GND PGND SC1480 C15 1uF C16 NO_POP R10 0 NO_POP R11 0 1 2 3 14 13 12 11 10 9 8 RGND C8 0.1uF 4 1 2 3 L1 R7 5 6 7 8 10K Q2 Si4884 4 4uH D2 MBRS140T3 + C10 150uF + C11 150uF C12 10uF/6.3V VOUT 1 2 J3 1.25V TP5 TP6 Q1 Si4884 D1 ZHCS400 C4 10uF/25V C5 10uF/25V C6 0.1uF SP1 C3 1uF R3 12.4K 1 GND R2 100 U1 SC431L R1 750 1.25V
PHASE_TP
PGD
R8 NO_POP
5 6 7 8
VOUT_TP
SP2
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SC1480
POWER MANAGEMENT Evaluation Board - Bill of Materials
Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Quantity 3 5 2 2 2 1 3 1 1 1 2 1 2 1 1 1 1 2 1 2 2 9 1 1 C1,C2,C12 C3,C7,C9,C13,C15 C4,C5 C6,C8 C10,C11 C 14 R8,R10,C16 D1 D2 J1 J2,J3 L1 Q1,Q2 R1 R2 R3 R4 R5,R6 R7 R9,R11 SP1,SP2 TP1 thru TP9 U1 U2 S C 431L S C 1480 Reference 10uF/6.3V 1uF 10uF/25V 0.1uF 150uF 1000pF NO_POP ZHCS400 MBRS140T3 Header Post Banana Jack 4uH S i 4884 750 100 12.4K 10 1M 10K 0 Probe test point Part
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SC1480
POWER MANAGEMENT Gerber Plots
Silk Screen Layer Bottom Layer
Power Ground Layer
Analog Ground Layer
Top Layer
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SC1480
POWER MANAGEMENT Typical Characteristic (Cont.)
SC1480EVB Efficiency at VOUT = 1.25V
100 95 90 0.6 0.5
SC1480EVB Line Regulation at VOUT = 1.25V
Line Regulation (%)
Efficiency (%)
85 80 75 70 65 60 0.1 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
VIN=25V VIN=14V VIN=4.5V
0.4
0.3
IOUT=0A IOUT=1A IOUT=2A IOUT=3A IOUT=4A IOUT=5A
0.2
0.1
0 4.5 10 14 19 25
Output Current (Amps)
Input Voltage (Volts)
SC1480EVB Load Regulation at VOUT = 1.25V
0.6 280 270 260 0.4 0.5
Frequency vs. Input Voltage (IOUT = 1A, VOUT = 1.25V, Rton = 1M)
Load Regulation (%)
Frequency (kHz)
5
250 240 230 220 210 200
0.3
0.2
0.1
VIN=4.5V VIN=10V VIN=14V VIN=19V VIN=25V
0 0 1 2 3 4
5
10
15
20
25
Load Current (Amps)
Input Voltage (Volts)
Frequency vs. Load Current (VIN = 15V, VOUT = 1.25V, Rton = 1M)
290 280
Rton vs. Frequency (VIN = 15V, VOUT = 1.25V, IOUT = 1A)
600 500
270
Frequency (kHz)
Frequency (kHz)
260 250 240 230 220 210 200 0 1 2 3 4 5 6
400
300
200
100
0 400
500
600
700
800
1000
1500
Load Current (Amps)
Rton (kohms)
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SC1480
POWER MANAGEMENT Typical Characteristic (Cont.)
Upper Trace: Phase Lower Trace: Output Ripple Voltage Upper Trace: 0A to +2A Transient Lower Trace: Output Ripple Voltage
Upper Trace: 0A to -2A Load Transient Lower Trace: Output Ripple Voltage
Upper Trace: 0A to +2A and 0A to -2A Transient Lower Trace: Output Ripple Voltage
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SC1480
POWER MANAGEMENT Marking Diagram Top Mark Bottom Mark
yy = two-digit year of manufacture ww = two-digit week of manufacture
xxxxxx = Wafer Lot Number xx = Assembly Lot Number
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SC1480
POWER MANAGEMENT Outline Drawing - TSSOP-14
A D
DIM
A A1 A2 b c D E1 E e L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .006 .002 .042 .031 .012 .007 .003 .007 .193 .197 .201 .169 .173 .177 .252 BSC .026 BSC .018 .024 .030 (.039) 14 0 8 .004 .004 .008 1.20 0.15 0.05 1.05 0.80 0.19 0.30 0.20 0.09 4.90 5.00 5.10 4.30 4.40 4.50 6.40 BSC 0.65 BSC 0.45 0.60 0.75 (1.0) 14 0 8 0.10 0.10 0.20
2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 B E
e
aaa C SEATING PLANE
D A2 A H GAGE PLANE 0.25 (L1) DETAIL SIDE VIEW SEE DETAIL L c
C bxN bbb
A1 C A-B D
01
A
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AB-1.
Land Pattern - TSSOP-14
X
DIM
(C) G Z C G P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .161 .026 .016 .061 .283 (5.65) 4.10 0.65 0.40 1.55 7.20
Y P
NOTES: 1.
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111 FAX (805) 498-3804 Visit us at: www.semtech.com
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